1. Field of the Invention
The present invention relates to a correlation double sampling circuit for an image sensor, and more particularly, to a correlation double sampling circuit having a simplified circuit structure and utilizing sampling capacitors that need not perform polarity inversion in operation for reducing noise.
2. Description of the Prior Art
As development of electronic products such as digital cameras and mobile phones progresses, the demand for image sensors increases accordingly. In general, image sensors in common usage nowadays are divided into two main categories: charge coupled device (CCD) sensors and CMOS image sensors (CIS). Primarily, CMOS image sensors have certain advantages of low operating voltages, low power consumption, and random access capability. Furthermore, CMOS image sensors are currently capable of integration with semiconductor fabrication processes. Based on those benefits, the application of CMOS image sensors has increased significantly.
Generally, the CMOS image sensor utilizes an analog front-end circuit to read out signals of each pixel sensor and to provide sufficient driving ability to drive rear-stage application circuits, such as analog to digital converters (ADCs) or image processors. In operation, a reset switch is utilized to reset the pixel sensor to an initial state for clearing remaining signals of a last operation. However, some reset noise may be injected when the reset switching is performed, and thus the industry further includes a correlation double sampling (CDS) circuit in the analog front-end circuit for separately sampling light-sensing signals and reset signals outputted from each pixel sensor, so that voltage level differences between the light-sensing signals and reset signals, i.e. the voltage level differences before and after exposure, can be obtained. Therefore, images of the CMOS image sensor can be isolated from impact of the reset noise.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional CMOS image sensor 10. The CMOS image sensor 10 includes a pixel array 11, a CDS circuit array 12 and a rear-stage buffer circuit 13. In general, the CDS circuit array 12 and the rear-stage buffer circuit 13 form the analog front-end circuit of the CMOS image sensor 10. As shown in FIG. 1, for convenience, a pixel sensor Pij represents a pixel sensor located at an ith column and a jth row of the pixel array 11, a CDS circuit CDS_i represents a CDS circuit coupled to all pixel sensors of the jth column, and the rear-stage buffer circuit 13 is coupled to all CDS circuits of the CDS circuit array 12. The pixel sensor Pij is an active pixel sensor with a four-transistor (4T) structure, and includes a photodiode PD, a transfer transistor TX, a reset transistor RX, a drive transistor DX and a select transistor SX. The photodiode PD is utilized for sensing incident light and accumulating photo charges that are generated due to the incident light. The transfer transistor TX is utilized for transferring the photo charges accumulated at the photodiode PD to a node FD according to a transfer control signal Tg1. The reset transistor RX is utilized for resetting a voltage of the node FD to a power supply voltage VDD according to a reset control signal Rst. The drive transistor DX is a source follower, and is utilized as a buffering amplifier for the select transistor SX. The select transistor SX is then utilized for successively outputting the reset signal and the light-sensing signal trough an output terminal PXO according to a row selection signal Rsel. Note that the transfer control signal Tg1, the reset control signal Rst and the row selection signal Rsel are generated by a row decoder, which is well known by those skilled in the art and not narrated herein.
The CDS circuit CDS_i is utilized for successively sampling the reset signals and the light-sensing signals outputted from all pixel sensors of the ith column, and includes sampling capacitors Cs and Cr, a constant current source I1, a reference voltage VR1 and eight switches 121˜128 respectively controlled by control signals SS, SR, Sn and Scel. The rear-stage buffer circuit 13 is coupled to the CDS circuit CDS_i via input terminals VIP and VIN, and includes an operational amplifier OP1, capacitors C1 and C2, and six MOSFET switches 131˜136 respectively controlled by control signals S1 and S2. The operation of the analog front-end circuit is briefly illustrated as follows. Firstly, the control signal Sn shorts the switches 123 and 124 to enable negative terminals of the sampling capacitors Cs and Cr to couple to the reference voltage VR1. Then, the control signals SR and SS successively short the switches 121 and 122 by two non-overlapping phases, so as to read out voltages of the reset signal and the light-sensing signal from the pixel sensor Pij and store the voltages into the sampling capacitors Cs and Cr. When the CMOS image sensor 10 is going to retrieve signals of the pixel sensor Pij, the switches 125˜128 and the switches 131, 132 are simultaneously shorted by the CDS circuit CDS_i and the rear-stage buffer circuit 13 according to the control signals Scel and S2, so as to convert polarities of the sampling capacitors Cs and Cr and transfer electric charges stored in the sampling capacitors Cs and Cr to the capacitors C1 and C2 of the rear-stage buffer circuit 13 by virtually grounding two input terminals of the operational amplifier OP1. Hence, the CMOS image sensor 10 can output a voltage signal Vout corresponding to a voltage difference between the reset signal and the light-sensing signal through differential output terminals VOP and VON for driving rear-stage data processors. Certainly, before the electric charges stored in the sampling capacitors Cs and Cr are transferred to the capacitors C1 and C2, the rear-stage buffer circuit 13 can further short the switches 133˜136 to clear remaining signals of last operation stored in the capacitors C1 and C2. As for related timing of the above control signals, please refer to FIG. 2.
For the analog front-end circuit of the CMOS image sensor, one chief design consideration is reduction of noise. The noise sources can be mainly classified into two kinds: thermal noise induced by operations of the sampling capacitors, and charge injection noise induced by switching the MOSFET switches. Since the thermal noise is proportional to KT/C (K: Boltzmann's constant, T: absolute temperature, and C: capacitance of sampling capacitor), the thermal noise can be improved by increasing the capacitance values of the sampling capacitors; and the charge injection noise can be lowered by reducing the number of the MOSFET switches and frequency of switching operations.